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数字锁相环作为广泛应用的一种频率合成技术,其相位噪声是关键的技术指标。本文对频率源相位噪声的原理进行了扼要阐述,然后从数字锁相环的相位噪声分析模型出发,讨论了环路带宽内和环路带宽外各部件对输出相位噪声的影响。以数字鉴相器ADF4110设计的锁相环为例,利用ADS软件进行电路仿真,进一步验证了分析结果,为数字锁相环的设计,提高相位噪声性能提供了参考依据。
Digital phase-locked loop as a widely used frequency synthesis technology, the phase noise is the key technical indicators. In this paper, the principle of frequency source phase noise is briefly described. Based on the phase noise analysis model of digital phase locked loop, the influence of each component within the loop bandwidth and the loop bandwidth on the output phase noise is discussed. Taking the phase locked loop designed by digital phase detector ADF4110 as an example, the circuit simulation is carried out by using ADS software to further verify the analysis results, which provides reference for the design of digital phase locked loop and the improvement of phase noise performance.