论文部分内容阅读
A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch &. decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was im1.8-V 1P6M process, with a core size of 2 mm×2mm .Result shows that it can run under 200MHz with a powerperformance around 0.3mW/MIPS.Meanwhile,only39.7% circuit is active simultaneously in average,comparedto its non-gating counterparts.