A survey of in-spin transfer torque MRAM computing

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In traditional von Neumann computing architectures,the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip.The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations.Among the different memory types,intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic mag-netic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node.This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell,circuit,and system levels.In addition,this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues.This study also considers the design technology co-optimization from the IMC perspective.
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