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本文对一种新的隔离方法进行了理论分析与计算.通过分析和计算的结果,我们给这种隔离方法定名为内偏压隔离,从而反映了这种隔离方法的物理实质.内偏压隔离,主要是利用p型和n型半导体相接触时所形成的接触电势差V_B(也称为扩散电势或内部偏压)的作用.V_B这个偏压是由载流子的扩散运动形成的.这个偏压的数值取决于杂质浓度和本征载流子浓度.在高补偿的晶体中,由于内偏压的作用,将展开一个较宽的耗尽区.当集成电路中外延层厚度相对薄时,这个耗尽区宽度可大于外延层厚度,从而切断外延层,以达到隔离外延层把外延层分成多个隔离岛的目的.这个隔离方法不需要单独的隔离区和单独的隔离扩散.只要适当的控制电路制作过程中的掺金量,使之形成较强的补偿,即可实现隔离.因此,这种隔离方法不但减少工艺程序、节省成本、减少设备,而且可以大大提高电路的集成度,提高电路的成品率.所以对中、大规模电路的研制和生产是有益的.采用这种工艺,可使TTL型的中、大规模电路在集成度方面与MOS电路,I~2L电路比美,而在速度方面却遥遥领先.
In this paper, a new method of isolation is theoretically analyzed and calculated. By analyzing and calculating the results, we named this method of isolation as internal bias isolation, which reflects the physical essence of this isolation method. Mainly utilizes the contact potential difference V_B (also referred to as diffusion potential or internal bias) formed when the p-type and n-type semiconductors are in contact with each other.V_B This bias is formed by the carrier diffusion. The value of the pressure depends on the impurity concentration and the intrinsic carrier concentration. In highly compensated crystals, a wider depletion region will unfold due to the effect of internal bias. When the thickness of the epitaxial layer in the integrated circuit is relatively thin, The width of the depletion region may be greater than the thickness of the epitaxial layer to cut off the epitaxial layer to achieve the purpose of isolating the epitaxial layer to divide the epitaxial layer into a plurality of isolated islands. This isolation method does not require separate isolation regions and separate isolation diffusion. Therefore, this isolation method not only reduces the process sequence, saves the cost, reduces the equipment, and can greatly increase the amount of gold in the control circuit fabrication process, so as to form strong compensation. The integration of the circuit, improve the yield of the circuit, so on the large-scale development and production of the circuit is beneficial to use this technology can make TTL-type, large-scale circuits in the integrated level with the MOS circuit, I ~ 2L circuit than the United States, but far ahead in terms of speed.