A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process

• 作 者: 杨兆年 刘红侠 王树龙
• 机 构: Key Laboratory of Wide Bandgap Semiconductor Materials and Devices of Ministry of Education,School o
• 出 处: Journal of Semiconductors
• 发表日期: 2013年04期
• 关键词: leakage trigger layout electrostatic circuits PMOS NMOS capacitor breakdown clam

An electrostatic discharge(ESD) detection circuit with a modified RC network for a 90-nm process clamp circuit is proposed.The leakage current is reduced to 4.6 nA at 25℃.Under the ESD event,it injects a 38.7 mA trigger current into the P-substrate to trigger SCR,and SCR can be turned on the discharge of the ESD energy.The capacitor area used is only 4.2μm~2.The simulation result shows that the proposed circuit can save power consumption and layout area when achieving the same trigger efficiency,compared with the previous circuits.

An electrostatic discharge (ESD) detection circuit with a modified RC network for a 90-nm process clamp circuit is proposed. The leakage current is reduced to 4.6 nA at 25 ° C. Under the ESD event, it injects a 38.7 mA trigger current into the P-substrate to trigger SCR, and SCR can be turned on the discharge of the ESD energy. The capacitor area used is only 4.2 μm ~ 2. The simulation result shows that the proposed circuit can save power consumption and layout area when achieving the same trigger efficiency, compared with the previous circuits.