Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

• 作 者: 王伟 胡瑜 韩银和 李晓维 张佑生
• 机 构: School of Computer and Information Hefei University of Technology Hefei 230009,China Key Laboratory
• 出 处: Journal of Computer Science & Technology
• 发表日期: 2007年05期
• 关键词: leakage portable sequential dissipation transistor optimize assignment specified

It is a well-known fact that test power consumption may exceed that during functional operation.Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor(CMOS)circuits during test has become a significant part of the total power dissipation.Hence,it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test,to increase test reliability and to reduce test cost.This paper analyzes leakage current and presents a kind of leakage current sinmlator based on the transistor stacking effect. Using it,we propose techniques based on don’t care bits(denoted by Xs)in test vectors to optimize leakage current in integrated circuit(IC)test by genetic algorithm.The techniques identify a set of don’t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector(MLV). Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage.

It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor (CMOS) circuits during test has become a significant part of the total power dissipation .ence , it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current sinmlator based on the transistor stacking effect. Using it, we propose techniques based on do not care bits (denoted by Xs) in test vectors to optimize leakage current in integrated circuit (IC) test by genetic algorithm. The techniques identify a set of do not care inputs in given test vectors and reassign specified logic values ​​to the X inputs by the genetic algorithm to get minimum leakage vector (MLV). Experimental results indicate that the techniques can effectually opti mize leakage current of combinational circuits and sequential circuits during test maintaining high fault coverage.