A Unified Buffering Management with Set Divisible Cache for PCM Main Memory

• 作 者: Mei-Ying Bian Su-Kyung Yoon Jeong-Geun Kim Sangjae Nam Shin-Dug Kim
• 机 构: Department of Computer Science, Yonsei University, Seoul 120-749, Korea
• 出 处: 计算机科学技术学报（英文版）
• 发表日期: 2016年1期
• 关键词: memory hierarchy memory structure cache memory buffer management

This research proposes a phase-change memory (PCM) based main memory system with an effective combi-nation of a superblock-based adaptive buffering structure and its associated set divisible last-level cache (LLC). To achieve high performance similar to that of dynamic random-access memory (DRAM) based main memory, the superblock-based adaptive buffer (SABU) is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer (SBPB) and an adaptive sub-block reusing buffer (SBRB), and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.