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这里将要叙述在一个单块基片上制造一个16×16位乘法器的设计、制造和测试。设计的这个片子,是用在一个体积小,速度快、多用途的处理机上。该处理机是为航空上应用研制的。这个乘法器是按2的补码数字系统设计的,以便同该处理机相一致。这个片子特有输出信号三状态缓冲器,和输入信号保留寄存器。这样的特点,不仅容许系统中的外引线可以分时,而且容许片子的信号引线分时,因而总的引线数减到32条数码线,4条控制信号线,加上几条电源和接地线。图1表示最普通的重复单元方案。通过这个方案的研究,能确定设计这种线路同大多数以前的电路的重要区别,就是每个部件的输出没有恢复逻辑电平。其原因是上升时间不可线
Here we will describe the design, manufacture, and testing of a 16 × 16-bit multiplier fabricated on a single substrate. The design of this film, is used in a small, fast, multi-purpose processor. The processor is developed for aerospace applications. This multiplier is based on a two’s complement digital system designed to be consistent with the processor. This chip has a unique output signal tri-state buffer, and input signal retention registers. This feature not only allows the system in the lead can be time-sharing, but also allows the film signal lead time-sharing, so the total number of leads reduced to 32 digital lines, 4 control signal lines, plus a few power and ground . Figure 1 shows the most common repeating unit scheme. Through the study of this program, we can determine the important difference between designing this circuit and most of the previous circuits, that is, the output of each component does not recover the logic level. The reason is that the rise time is not linear