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1简介芯片的设计尺寸和复杂度不断增加,功耗约束越来越苛刻,导致芯片内异步时钟爆炸性增长。由于错误的异步信号传输设计将会导致许多在单时钟域设计中不曾出现的问题,因此,设计和验证团队不得不花费大量的时间来验证芯片异步信号传输设计的正确性。亚稳态(Metastability)是其中主要的一个问题。如果触发器的输入数据在时钟跳变沿附近很小的时间窗口内发生改变,从而导致无法预测输出何时才
1 Introduction The design size and complexity of the chip are increasing, and the power constraints are more and more harsh, resulting in an explosive growth of the asynchronous clock in the chip. Designing and verifying teams have to spend a lot of time verifying the design of asynchronous signaling in chips due to the wrong design of asynchronously transmitted signals, which will lead to many problems not encountered in single-clock domain designs. Metastability is one of the major issues. If the trigger’s input data changes within a small time window near the edge of the clock, unpredictable output will result