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提出了“可预置计数限的计数逻辑”和“有暂停控制的双向计数器逻辑”,解决了VME总线主板所能处理的中断的频率与输入信号脉冲的频率不匹配的难题,消除了某些信号与系统时钟异步造成的准稳态;所设计的插件实现了VME总线程控流水线式发中断的功能.
“Counting logic for presettable count limits” and “Bidirectional counter logic for suspend control” are proposed to solve the problem that the frequency of the interrupts that can be handled by the VME bus board does not match the frequency of the input signal pulses, eliminating some Signal and system clock caused by asynchronous quasi-steady-state; designed plug-ins to achieve the VME bus programmable interrupt pipeline function.