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介绍了一种基于双通道采样保持电路的流水线操作 AD变换器。设计结合了并行流水线转换电路的思想 ,从而能够有效提高转换速率 ,但是较之并行流水线结构 ,使用的运放较少 ,功耗低 ,而且可以避免并行结构可能存在的匹配问题。这个电路采用 0 .3 5 μm CMOS工艺实现 ,在 Cadence Spectre S环境下通过仿真验证 ,转换速率 40 MS/s时 ,能达到 1 0位精度
A pipeline operation AD converter based on dual-channel sample-and-hold circuit is introduced. The design incorporates the idea of a parallel pipeline conversion circuit, which can effectively improve the slew rate, but compared to the parallel pipeline architecture, the use of less op amp, low power consumption, but also to avoid the parallel structure may exist matching problem. This circuit is implemented in a 0.35 μm CMOS process and is emulated in the Cadence Specter S environment to achieve 10-bit accuracy at 40 MS / s conversion rate