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本文对LVDS的时钟位嵌入式构架模式和交流耦合进行了简要说明,并对时钟位嵌入式架构的驱动器和接收器实现交流耦合的可行性进行了分析,最终通过实际测试,完成了一对时钟位嵌入式架构LVDS芯片的交流耦合。
In this paper, a brief description of the LVDS clock bit embedded architecture and AC coupling is given, and the feasibility of AC coupling between the clocked bit embedded architecture driver and the receiver is analyzed. Finally, a pair of clocks AC-Coupling of Bit-Embedded LVDS Chip.