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乘法器是数字信号处理系统中的关键。流水线乘法器可以以较小的代价获得较高的平均速度。本文给出了流水线乘法器的结构;提出了两种改进型Domino加法器电路;对改进型电路作了分析和模拟。模拟结果表明,采用新的改进型Domino电路后,流水线乘法器的速度可以显著提高。
Multipliers are the key to digital signal processing systems. Pipeline multipliers can get a higher average speed at a lower cost. This paper presents the structure of a pipeline multiplier; two improved Domino adder circuits are proposed; and the improved circuit is analyzed and simulated. Simulation results show that with the new improved Domino circuit, the pipeline multiplier speed can be significantly improved.