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提出了一种由三相电源驱动的新绝热逻辑电路—— complementary pass- transistor adiabatic logic (CPAL ) .电路由 CPL电路完成相应的逻辑运算 ,由互补传输门对输出负载进行绝热驱动 ,电路的整体功耗较小 .指出选取合适的输出驱动管的器件尺寸可进一步减小 CPAL电路的总能耗 .设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路 .为了验证提出的 CPAL电路和时钟产生电路 ,设计了 8bit全加器进行模拟试验 .采用 MO-SIS的 0 .2 5μm CMOS工艺 ,在 5 0～ 2 0 0 MHz频率范围内 ,CPAL全加器的功耗仅为 PFAL电路和 2 N - 2 N2 P电路的 5 0 %和 35 % .
A new adiabatic logic circuit (CPAL) driven by three-phase power is proposed. The CPL circuit completes the corresponding logic operation, and the output of the load is adiabatically driven by the complementary transmission gate. The whole circuit The power consumption is small.It is pointed out that the size of the device selected by the appropriate output drive tube can further reduce the total energy consumption of the CPAL circuit.The three-phase power clock generation circuit consists of only one inductor and a simple control circuit.To verify the proposed CPAL Circuit and clock generation circuit, an 8-bit full adder is designed to simulate the experiment.Using MO-SIS 0.52 CMOS technology, CPAL full adder consumes PFAL only in the frequency range of 50 ~ 200 MHz 50% and 35% of circuits and 2 N - 2 N2 P circuits.