论文部分内容阅读
单管单元随机存取存贮器(即RAM)的容量,由于信号在读出周期中的衰减而受到限制。现在电荷耦合线路(即CCD)能获得最高的存贮密度,但是,采用这种工艺又招致RAM 的主要优点一随机存取的丧失。西门子公司终于制成既有CCD 存贮器的存贮密度,同时又保留随机存取特性的半导体存贮器。这种C~3RAM(Continiously Charge-Coupled Random Access Memory)含有由单管单元组成的存贮器(见图)。各个单元均被连在一条以MOS 传输连线形式出现的共同位线上,该线接在写/读放大器的侧端。初步试验表明,在300微米的MOS 传输线上,渡越时间约为250毫微秒。就封装在标准管壳里的芯片而言,该电路的理论存贮密度为32K 位。写/读全周期约为1微秒。
The capacity of a single-pipe random access memory (RAM) is limited by the attenuation of the signal during the read-out period. Charge-coupled lines (CCDs) now yield the highest storage densities, but the use of this process again leads to the main advantage of RAM, the loss of random access. Siemens has finally made a semiconductor memory that combines both the memory density of a CCD memory and the random access features. The C-3RAM (Continuallyly Charge-Coupled Random Access Memory) contains a memory consisting of a single tube unit (see figure). Each cell is connected to a common bit line in the form of a MOS transmission line that is connected to the side of the write / read amplifier. Preliminary tests showed that transit time was about 250 nanoseconds on a 300-micron MOS transmission line. In the case of a chip packaged in a standard package, the theoretical storage density of this circuit is 32K bits. Write / read full cycle is about 1 microsecond.