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介绍了Viterbi译码算法SoftCoreIP的一种低功耗实现方案,对其中的核心功能单元ACS(Adder_Compare_Select)提出了一种改进的设计结构,并介绍了电路时钟的优化技术及低功耗设计技术,经实验证明,确实达到了降低功耗、减小电路规模的设计目的。
A low-power implementation scheme of Viterbi decoding algorithm SoftCoreIP is introduced. An improved design structure is proposed for the core function unit ACS (Adder_Compare_Select). The circuit clock optimization technology and low power consumption design technique are introduced. Proved by experiments, it has indeed reached the design goal of reducing power consumption and reducing the circuit scale.