A pipelined architecture for normal I/O order FFT

• 出 处: Journal of Zhejiang University-Science C(Computers & Electro
• 发表日期: 2011年01期
• 关键词: radix hardware producing usage capable imaginary Electron throughput requirement

We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order.A single-path delay commutator processing element (SDC PE) has been proposed for the first time.It saves a complex adder compared with the typical radix-2 butterfly unit.The new pipelined architecture can be built using the proposed processing element.The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs.In order to produce the output sequence in normal order,we also present a bit reverser,which can achieve a 50% reduction in memory usage.

We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared the new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.