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面向存在低耗电要求的数字家电SoC(系统芯片),东芝日前试产了栅长10nm的晶体管。在2004年6月15日于美国檀香山开幕的半导体制造技术国际会议“2004 Symposium on VLSI Technology”上进行了技术发表。“目前已经证实晶体管能够正常开关,泄漏电流处在大体允许的范围内”(东芝)。设计工艺为22nm,预计2016年前后开始量产。其最大特点是采用了与现有技术相同的Bulk MOS结构晶体管,而不是SOI和Fin
For low-power digital consumer SoC (system-on-chip) with low power requirements, Toshiba recently produced a 10nm gate length of the transistor. The technology was presented at the 2004 Symposium on VLSI Technology conference at the International Conference on Semiconductor Manufacturing Technology that opened in Honolulu on June 15, 2004. “It has now been confirmed that the transistor can be normally switched, the leakage current is within the generally allowable range” (Toshiba). The design process is 22nm and mass production is expected before and after 2016. Its most prominent feature is the use of the same state of the art Bulk MOS transistor structure, rather than SOI and Fin