论文部分内容阅读
本文介绍由绝缘栅场效应晶体管(IGFET)开关电容存储单元组成一个全动态译码、1024字×1位的P沟道随机存储器。采用10伏的驱动电路,测得芯片取数时间为150 ns,周期时间为300ns。当周期为300ns时测得通导芯片的功耗低于80毫瓦(80微瓦/单元),而在较低速度时其功耗更小。它在100℃时恢复功率低于1微瓦/单元。在准平衡设计中,两个16行×32列存储单元矩阵由选通触发器的电荷敏感器及读写电路所膈离。存取一个矩阵中的一行单元及采用另一不工作的矩阵去平衡共式信号并允许通导芯片可靠鉴别存储电荷。到敏感器的标称输入信号估计为±2V。可以快速关闭且也考虑到单元电荷的变化和触发器阀值的不平衡。平衡读写电路可从芯片取出读出信号进行差动鉴别。译码电路使用单线二进制地址输入使通导芯片的动态地址反向。制造工艺采用具有离子注入源、漏和沟道夹断的P沟道自对准栅。采用两层钨金属化系统,它具有磷玻璃和氮化硅及非电镀金梁式引线。设计和加工结果得到了小单元面积(用10微米的设计规则,面积低于5密耳~2),每单元仅半个结点,由于第二层金属清晰度仅用四道光刻步骤就可得到高成品率,阀值电压的相对不灵敏性变化为±(1/2)伏,以及取数和周期时间短,工作压降低(10伏)及功耗低。该存储器芯片已完成了设计、制造和测试。其芯片由1024个开关电容存储单元组成,与取数电路有关的包括有地址译码、选通触发器鉴别恢复及读写电路。设计的主要目的在于高速、低功耗、宽工作容限和制造方便。为满足这些目的而采用了准平衡设计、动态译码电路和相当大的光刻容差。
This article describes a full-dynamic decoding, 1024 words × 1-bit P-channel random access memory (SRAM) cell made up of IGFET switched capacitor cells. Using 10-volt drive circuit, measured the chip take time is 150 ns, the cycle time is 300ns. The pass-chip power consumption was measured to be less than 80 milliwatts (80 microwatts / cell) at a period of 300 ns, while it consumes less power at lower speeds. It recovers less than 1 microwatt / cell at 100 ° C. In a quasi-balanced design, two 16-by-32 columns of memory cell matrices are separated by the strobe trigger’s charge sensor and read-write circuitry. Access one row of cells in one matrix and use another inactive matrix to balance the common signal and allow the via chip to reliably identify the stored charge. The nominal input signal to the sensor is estimated as ± 2V. It can be switched off quickly and also takes account of changes in cell charge and unbalance of the trigger threshold. Balance read and write circuit can read out the signal from the chip for differential identification. The decoding circuit uses single-wire binary address input to reverse the dynamic address of the pass-through chip. The fabrication process uses a P-channel self-aligned gate with ion source, drain, and channel pinch-off. Two-layer tungsten metallization system with phosphor glass and silicon nitride and non-plated gold beam leads. The design and processing results yield small cell area (with 10 micron design rule, area less than 5 mils ~ 2) and only half a node per cell, since the second level of metal definition is achieved using only four lithography steps High yields are achieved with a relative ± 1 / 2V change in threshold voltage, short take-up and cycle times, low operating voltage (10V), and low power consumption. The memory chip has been designed, manufactured and tested. The chip consists of 1024 switch capacitor storage unit, and access circuits include address decoding, strobe trigger recovery and read and write circuits. The main purpose of the design is high speed, low power consumption, wide work tolerance and easy manufacture. To meet these goals, a quasi-balanced design, dynamic decoding circuitry and considerable photolithographic tolerances are used.