A write buffer design based on stable and area-saving embedded SRAM for flash applications

• 作 者: CAO Hua Min HUO Zong Liang WANG Yu LI Ting LIU Jing JIN Lei JIANG Dan-Dan ZHANG Deng Jun LI Di LIU Ming
• 机 构: Institute of Microelectronics, Chinese Academy of Sciences,College of Communication Engineering, Che
• 出 处: Science China(Technological Sciences)
• 发表日期: 2015年02期
• 关键词: write saving timing Figure verified throughput corners correctly accomplish wave

This paper presents an embedded SRAM design for write buffer applications in flash memories.The write buffer is implemented with a newly proposed self-adaptive timing control circuit,an area-saving sense-latch circuit and 6 T SRAM cell units.A 2 kb SRAM macro with the area of 135μm×180μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory process.Both simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.

This paper presents an embedded SRAM design for write buffer applications in flash memories. The write buffer is implemented with a newly proposed self-adaptive timing control circuit, an area-saving sense-latch circuit and 6 T SRAM cell units. A 2 kb SRAM macro with the area of ​​135 μm × 180 μm is implemented in and applied to a 128 Mb NOR flash memory with SMIC 65 nm NOR flash memory process. B. simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.