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先进集成电路工艺下,时延测试是数字电路测试的一项重要内容。各种时延偏差来源如小时延缺陷、工艺偏差、串扰、电源噪声、老化效应等,影响着电路的额定时钟频率,是时延测试中需要考虑的因素。文章在介绍电路时延偏差问题的各种来源的基础上,给出了针对不同的时延偏差问题所涉及的分析、建模、测试生成与电路设计等关键技术。进一步介绍了中国科学院计算技术研究所近年来在考虑时延偏差的数字电路时延测试方面所做的研究工作,包括:考虑串扰/电源噪声的时延测试、基于统计定时分析的测试通路选择、片上时延测量、超速测试、测试优化、在线时序检测等方面。文章最后对数字电路时延测试技术的发展趋势进行了总结。
Advanced integrated circuit technology, the delay test is an important part of digital circuit testing. Various sources of delay variation, such as small delay defects, process variations, crosstalk, power supply noise, aging effects, affect the rated clock frequency of the circuit and are factors to consider in the delay test. After introducing various sources of circuit delay deviation problems, the paper presents the key technologies of analysis, modeling, test generation and circuit design for different time delay deviations. In this paper, the research work done by Institute of Computing Technology, Chinese Academy of Sciences, in recent years on the delay of digital circuits with delay variation is introduced, including the following: delay considering crosstalk / power supply noise, selecting test path based on statistical timing analysis, On-chip delay measurement, speeding test, test optimization, online timing detection and so on. Finally, the article summarizes the development trend of digital circuit delay testing technology.