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系统阐述了基于纯软件算法的三相同步锁相环(Synchronous Reference Frame Phase-Locked Loop,SRF-PLL)的原理。通过分析其抗扰性能,指明无须额外的结构改进(如增加数字滤波、提高系统阶数等),只要优化设计合适的环路滤波器参数,就可以实现目标电压在三相不平衡和畸变条件下的精确锁相。通过MatlabSISOTOOL工具进行参数设计,分别在基于Simulink的软件平台和TMS320C6713芯片的硬件平台上,进行了仿真和实验的论证。实验中将参数优化设计锁相环与加数字
The principle of Synchronous Reference Frame Phase-Locked Loop (SRF-PLL) based on pure software algorithm is systematically described. By analyzing its anti-jamming performance, indicating that no additional structural improvements (such as increasing the number of filters to improve the system order, etc.), as long as the optimal design of the appropriate loop filter parameters, you can achieve the target voltage in the three-phase imbalance and distortion conditions Precise phase under the lock. The parameters were designed by MatlabSISOTOOL tool, and the simulation and experiment were carried out on the hardware platform based on Simulink and TMS320C6713 respectively. In the experiment, the parameters are optimized to design PLL and digital