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根据基2分解的FFT算法理论,采用了流水线与并行结合的方式,设计了一种基于FPGA芯片的FFT计算模块.该模块由地址控制单元和存储单元配合蝶形运算单元,实现了计算长度为1 024点、数据类型为32位浮点型的FFT计算.测试结果表明,该模块在CycloneIII芯片中耗用3 928个LE和123kb的存储器资源,稳定工作频率可达110 MHz,完成1 024点FFT变换时间为95.66μs,具有良好的运算性能.
According to the theory of FFT algorithm based on radix-2 decomposing, an FFT computation module based on FPGA chip is designed by combining pipeline and parallel.The module consists of address control unit and storage unit cooperate with butterfly computing unit, 1 024 data type 32-bit floating-point FFT calculation.The test results show that the module consumes 3 928 LEs and 123kb memory resources in the CycloneIII chip, stable operating frequency up to 110 MHz, the completion of 1 024 points FFT transform time is 95.66μs, with good computing performance.