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High permittivity materials have been required to replace traditional SiO_2 as the gate dielectric to extend Moore’s law.However,growth of a thin SiO_2-like interfacial layer(IL) is almost unavoidable during the deposition or subsequent high temperature annealing.This limits the scaling benefits of incorporating high-k dielectrics into transistors.In this work,a promising approach,in which an O-scavenging metal layer and a barrier layer preventing scavenged metal diffusing into the high-k gate dielectric are used to engineer the thickness of the IL,is reported. Using a Ti scavenging layer and TiN barrier layer on a HfO_2 dielectric,the effective removal of the IL and almost no Ti diffusing into the HfO_2 have been confirmed by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy.
High permittivity materials have been required to replace traditional SiO_2 as the gate dielectric to extend Moore’s law. However, growth of a thin SiO_2-like interfacial layer (IL) is almost unavoidable during the deposition or subsequent high temperature annealing. Here limits the scaling benefits of incorporating high-k dielectrics into transistors. this work, a promising approach, in which an o-scavenging metal layer and a barrier layer preventing scavenged metal diffusing into the high-k gate dielectric are used to engineer the thickness of the IL, is reported. Using a Ti scavenging layer and TiN barrier layer on a HfO 2 dielectric, the effective removal of the IL and almost no Ti diffusing into the HfO_2 have been confirmed by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy.