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本文以电容线性延时模型为基础，通过分析逻辑电路在综合及布图阶段的延时计算方式，提出了一种在工艺映射与布局合并算法中动态估计电路延时的方法，并给出实验结果。
In this paper, based on the capacitive linear delay model, a method of dynamically estimating the circuit delay in process mapping and layout combining algorithm is proposed by analyzing the delay calculation method of logic circuit in the synthesis and layout stages, and the experiment result.