论文部分内容阅读
在数字通信中用锁相环路提取同步信号及载波信号时,实现初始捕捉是个重要问题。要想抑制相位抖动,就要使频带变窄。可是,环路带宽一变窄,就要影响同步和初始捕捉,这一点对于数字锁相环路也无例外。本文介绍的这个方案是在一般的二值量化锁相环路DPLL中外加初始捕捉环路,不但控制了稳态特性的劣化,而且实现了初始捕捉,把这个新的锁相环路叫做DPLL—pf。实验结果和理论分析表明,该环路的同步带变宽且实现了初始捕捉。
In the digital communications using phase-locked loop to extract the synchronization signal and the carrier signal, the realization of the initial capture is an important issue. To suppress phase jitter, it is necessary to narrow the band. However, as soon as the bandwidth of the loop becomes narrower, synchronization and initial capture are affected, which is no exception to the digital phase-locked loop. The scheme introduced in this paper is to add an initial capture loop to the general binary phase-locked loop DPLL to not only control the deterioration of the steady-state characteristics but also realize the initial capture. The new phase-locked loop is called DPLL- pf. The experimental results and theoretical analysis show that the synchronous belt of the loop is widened and the initial capture is achieved.