论文部分内容阅读
在宽带分频器中,采用电流模逻辑-D触发器(CML-DFF)结构,加入了并联峰化电感和频率调节电路。分析了CML-DFF分频器的基本工作原理,引入了一种新颖的分析模型。以此模型为基础,设计了一种带峰化电感的宽带可调CML-DEF分频器,提高了电路的设计效率,优化了电路性能。采用TSMC 90nm射频CMOS工艺仿真,结果显示,在0dBm输入信号下,分频器电路的可调节频率锁定范围为3~46.5GHz,芯片面积小于0.22mm2,功耗仅为6.7mW。
In the broadband divider, the current mode logic-D flip-flop (CML-DFF) structure, joined the parallel peaking inductance and frequency adjustment circuit. The basic working principle of CML-DFF divider is analyzed, and a novel analysis model is introduced. Based on this model, a broadband tunable CML-DEF divider with peaking inductance is designed, which improves the design efficiency and optimizes the circuit performance. Using TSMC 90nm RF CMOS process simulation, the results show that the adjustable frequency lock range of the divider circuit is 3 ~ 46.5GHz under 0dBm input signal, the chip area is less than 0.22mm2, and the power consumption is only 6.7mW.