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A low on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) n-channel lateral double-diffused metal-oxide-semiconductor(LDMOS) is proposed and its mechanism is investigated by simulation.The LDMOS has two features:the integration of a planar gate and an extended trench gate(double gates(DGs));and a buried P-layer in the N-drift region,which forms a triple reduced surface field(RESURF)(TR) structure.The triple RESURF not only modulates the electric field distribution,but also increases N-drift doping,resulting in a reduced specific on-resistance(Ron,sp) and an improved breakdown voltage(BV) in the off-state.The DGs form dual conduction channels and,moreover,the extended trench gate widens the vertical conduction area,both of which further reduce the Ron,sp.The BV and Ron,sp are 328 V and 8.8 m.cm2,respectively,for a DG TR metal-oxide-semiconductor field-effect transistor(MOSFET) by simulation.Compared with a conventional SOI LDMOS,a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%.The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit,thereby saving the chip area and simplifying the fabrication processes.
A low on-resistance (Ron, sp) integrable silicon-on-insulator (SOI) n-channel lateral double- diffused metal-oxide- semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure.The triple RESURF not only modulates the electric field distribution but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron, sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and , moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron, sp. BV and Ron, sp are 328 V and 8.8 m.cm2, respectively, for a DG TR metal-oxide-semiconductor field -effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device par ameters as those of DG TR MOSFET reduces Ron, sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit so saving the chip area and simplifying the fabrication processes.