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据日本《电子材料》1993年第2期报道,日本NEC公司采用0.25μm微细加工技术已研制成世界上最小单元面积(0.54μm~2)256M DRAM用的存储单元,其主要特点如下: (1)把以前的单层位线做成双层SLDB(Split-Level Diagonal Bit Line)存储单元结构,制成0.54μm~2的最小单元面积,已可实现芯片尺寸小型化和低成本。 (2)在硅衬底上,腐蚀具有斜度的沟道,在沟道中,填充(?)状硅氧化膜,实现器件隔离;由于大幅度降低位线电容,单元可稳定工作,与此同时,可实现芯片尺寸小型化。 (3)将信息转为电荷,使积蓄电容电极的形状制成圆筒状,再采用把其表面制成凹凸化的HSG技术,不提高电极高度,且能增大电容部分的面积,充分保证电容值(30fF),已实现稳定
According to Japan’s “Electronic Materials” No. 2, 1993 reported that Japan’s NEC 0.25μm microfabrication technology has been developed into the world’s smallest unit area (0.54μm ~ 2) 256M DRAM memory cells, the main features are as follows: (1 ) By forming a single layer bit line into a double-layer SLDB (Split-Level Diagonal Bit Line) memory cell structure to a minimum unit area of 0.54 μm to 2, chip size reduction and cost reduction have been achieved. (2) etching a trench with a slope on a silicon substrate, filling a silicon oxide film in the trench to isolate the device, and stabilizing the cell due to the drastic reduction of the bit line capacitance , Chip size can be miniaturized. (3) The information is converted to electric charges so that the shape of the storage capacitor electrode is formed into a cylindrical shape, and then the surface of the storage capacitor electrode is made of a so-called HSG technology that does not increase the height of the electrode and increases the area of the capacitor portion. Capacitance (30fF), has achieved stability