A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filte

• 作 者: C. ARUN V. RAJAMANI
• 机 构: 不详
• 出 处: 通讯、网络与系统学国际期刊(英文)
• 发表日期: 2009年6期
• 关键词: VITERBI DECODER Convolutional Codes High-Speed Low Power Consumption Parallel Pr

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have bee