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本文系统地分析了按常规设计步骤得到的111系列检测器的时序。指出电路对输入信号有严格限制。为放宽限制对电路作如下修改:对用主—从J—κ触发器的电路,用CP取样输出;对用维一阻型D触发器的电路,则以CP作触发器的触发信号,并以CP取样取出。还指出这些分析和修改在另外一些情况下同样适用。对一些资料上的提法有不同意见。
This paper systematically analyzes the timing of the 111-series detectors that were obtained by conventional design steps. Pointed out that the circuit has strict restrictions on the input signal. In order to relax restrictions on the circuit to make the following changes: For the main - from the J-κ flip-flop circuit, with the CP sampling output; for the use of a resistance D flip-flop circuit, then the trigger signal for the trigger CP Take CP samples and remove. It is also pointed out that these analyzes and modifications also apply in other cases. There are different opinions on some of the references to the information.