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将电源电压降低到晶体管阈值电压附近可以有效提高数字电路的能效,而近阈值标准单元库是近阈值数字电路设计的基础。通过分析逻辑门间静态噪声容限的兼容性、逻辑门在宽电压范围下延时变化情况,并通过求解最大包问题等的相关算法,对现有的商用数字CMOS标准单元库进行有效筛选,得到适用于低电压工作的近阈值数字CMOS标准单元库。通过一个应用于传感网中的双电压域、双核微控制器流片测试,对此标准单元库进行了验证,结果显示其中工作在0.5 V下的高能效核的能量效率相较传统工作电压下提高到2.76倍。
Lowering the supply voltage to near the threshold voltage of a transistor can effectively improve the energy efficiency of the digital circuit, while the near-threshold standard cell library is the basis for the near-threshold digital circuit design. By analyzing the compatibility of static noise margin between logic gates, the delay of logic gate under wide voltage range is extended, and the existing commercial digital CMOS standard cell library is effectively screened through the algorithm of solving the maximum packet problem. Get near threshold digital CMOS standard cell library for low voltage operation. Through a dual-voltage domain, dual-core microcontroller chip test applied to the sensor network, the standard cell library was verified. The results show that the energy efficiency of the energy-efficient core operating at 0.5 V is lower than the traditional working voltage Up to 2.76 times under.