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This paper presented an implementation of a direct sequence spread spectrum transmitter, which used FPGA as a hardware platform, and Max- plusII as a design tool. And the modules were designed using Verilog HDL and the top layer was designed based on graphical method. In this design, Bits to be transmitted are read from ROM circularly, and the channel coding utilizes (2,1,7) convolution codes. The spread spectrum module adopted kasami codes with a spread length 255. And a 3 bit quantization is used for polar transformation. Between every bit, 7 bits were inserted in interpolation module. The output filter is a 16 level FIR filter. The Verilog HDL codes, block diagram of the whole system, and the simulation results were presented in this paper. The result of the simulation showed that this is a high accurate and stable design without any glitch.
This paper presented an implementation of a direct sequence spread spectrum transmitter, which used FPGA as a hardware platform, and Max-plus II as a design tool. And the modules were designed using Verilog HDL and the top layer was designed based on graphical method. In this design, Bits to be transmitted are ROM circularly, and the channel coding utilizes (2,1,7) convolution codes. The spread spectrum module adopted kasami codes with a spread length 255. And a 3 bit quantization is used for polar transformation. Between every bit, 7 bits were inserted in interpolation module. The output filter is a 16 level FIR filter. The Verilog HDL codes, block diagram of the whole system, and the simulation results were presented in this paper. simulation showed that this is a high accurate and stable design without any glitch.