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The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18- m one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature(PVT) variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 d B,while an ideal value is 21.072 d B. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure.
The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized ACCulator based on 0.18-m one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature (PVT) variations. layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 d B, while an ideal value of 21.072 d B. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. furthermore, it is promising to design a higher stage accumulator based on the proposed structure.