Xilinx:选择FPGA设计的测试策略

• 出 处: 电子设计技术
• 发表日期: 2004年期
• 关键词: 逻辑分析仪 测试策略 逻辑分析 内部存储器 逻辑电路 示波器 时钟速率 超高密度 数据采集 逻辑设计

测试和验证超高密度逻辑设计有两种方法。传统的方法是使用逻辑分析仪、示波器和总线分析仪,通过测试头和连接器把信号送到仪器上。另一种方法是在FPGA设计中插入逻辑分析核,它具有普通逻辑分析仪的功能,包括触发、数据采集和存储等。利用逻辑分析核,用户可以访问FPGA器件内部所有信号和节点。来自内部逻辑电路的信号可以通过FPGA中的高速互连转移到内部存储器。这些信号以系统时钟速率传送,

There are two ways to test and verify ultra-high-density logic designs. Traditionally, logic analyzers, oscilloscopes, and bus analyzers were used to send signals to the instrument via test heads and connectors. Another approach is to insert a logic analyzer core in an FPGA design that has the power of a normal logic analyzer, including triggering, data acquisition and storage. With a logic analyzer core, users have access to all signals and nodes inside the FPGA device. Signals from internal logic can be transferred to internal memory through high-speed interconnects in the FPGA. These signals are transmitted at the system clock rate,