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软错误由高能粒子撞击所产生,对处理器的可靠性产生很大的损害.随着处理器设计目标转向低功耗、高性能和低供电电压,软错误的发生日益频繁,处理器的可靠性研究也随之受到越来越多的关注.针对传统的基于注错仿真的可靠性评估方法效率低的缺陷,提出了一套系统的cache可靠性评估方法,以可靠性指标之一---体系结构易受损因子(architectural vulnerability factor,AVF))---为研究对象,一方面,基于指令行为分析应用程序运行过程中对最终结果不产生影响的指令,从而确定对cache的AVF产生作用的指令;另一方面,根据cache的存储类型、所采取的写策略,结合cache中数据/指令阵列和地址标识阵列的特点,对cache上的各种相邻操作组合对AVF的影响进行了研究,从而完成AVF评估所需的信息分析.实验部分对PISA体系结构指令cache中的指令阵列进行了AVF评估,说明了该方法的有效性.
Soft errors are caused by collisions with high-energy particles, which can be very damaging to the processor’s reliability. As processor designs move to lower power, higher performance, and lower supply voltages, soft errors occur more frequently and processor reliability More and more attention has been paid to the research of sexuality.Aiming at the defect of low efficiency of the traditional reliability assessment method based on error simulation, a set of systematic cache reliability assessment method is proposed, - Architectural vulnerability factor (AVF)) --- is the object of study, on the one hand, to analyze the instruction that does not affect the final result during the operation of the application based on the instruction behavior to determine the AVF generation to the cache On the other hand, according to the storage type of cache and the strategy of writing, the influence of various adjacent operation combination on AVF is carried out according to the characteristics of data / instruction array and address identification array in cache Research, to complete the AVF assessment required for the information analysis.Experimental part of the PISA architecture instruction cache instruction array AVF evaluation, illustrates the effectiveness of the method.