【摘 要】
：
设计了一个5.156 25GHz低抖动、低杂散的亚采样锁相环,使用正交压控振荡器产生4路等相位间隔时钟。分析了电荷泵的杂散理论,使用差分缓冲器和互补开关对实现了低杂散。使用Du
【机 构】
：
中国科学技术大学微纳电子系统集成研究中心,
论文部分内容阅读
设计了一个5.156 25GHz低抖动、低杂散的亚采样锁相环,使用正交压控振荡器产生4路等相位间隔时钟。分析了电荷泵的杂散理论,使用差分缓冲器和互补开关对实现了低杂散。使用Dummy采样器和隔断缓冲器,进一步减小了压控振荡器对杂散的恶化。该亚采样锁相环在40nm CMOS工艺下实现,在1.1 V的供电电压下,功耗为7.55 mW;在156.25 MHz频偏处,杂散为-81.66dBc;亚采样锁相环输出时钟的相位噪声在10kHz~100 MHz区间内积分,得到均方根抖动为0.26ps。
A 5.156 25GHz, low jitter, low-spurious sub-sampling phase-locked loop is designed using a quadrature voltage-controlled oscillator to generate 4 equal-phase spaced clocks. The charge pump spurious theory is analyzed and low spurs are achieved using differential buffers and complementary switch pairs. The use of Dummy samplers and isolation buffers further reduces the VCO’s susceptibility to spurs. The sub-sampling phase-locked loop is implemented in a 40nm CMOS process with a power dissipation of 7.55 mW at 1.1 V supply voltage and -81.66 dBc spurious at 156.25 MHz frequency offset. The phase of the sub-sampling phase-locked loop output clock The noise is integrated in the 10 kHz to 100 MHz range to give a root mean square jitter of 0.26 ps.
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