【摘 要】
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High-resistivity silicon-on-insulator (HR-SOI) and trap-rich high-resistivity silicon-on-insulator (TR-SOI) substrates have been widely adopted for high-perform
【机 构】
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State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and
论文部分内容阅读
High-resistivity silicon-on-insulator (HR-SOI) and trap-rich high-resistivity silicon-on-insulator (TR-SOI) substrates have been widely adopted for high-performance rf integrated circuits.Radio-frequency loss and nonlinearity characteristics are measured from coplanar waveguide (CPW) transmission lines fabricated on HR-SOI and TR-SOI substrates.The patted insulator structure is introduced to reduce loss and non-linearity characteristics.A metal-oxide-semiconductor (MOS) CPW circuit model is established to expound the mechanism of reducing the parasitic surface conductance (PSC) effect by combining the semiconductor characteristic analysis (pseudo-MOS and C V test).The rf performance of the CPW transmission lines under dc bias supply is also compared.The TR-SOI substrate with the patted oxide structure sample has the minimum rf loss (＜ 0.2 dB/mm up to 10 GHz),the best non-linearity performance,and reductions of 4 dB and 10 dB are compared with the state-of-the-art TR-SOI sample’s,HD2 and HD3,respectively.It shows the potential application for integrating the two schemes to further suppress the PSC effect.
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