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研究了小波包变换的硬件实现问题。针对现有小波变换硬件实现方案存在的适用范围窄、不适用于长支集小波和高分解级数等缺点，提出了基于双缓冲存储区的小波包变换硬件架构。其具有一定的可编程性和通用性，并以此为基础设计了通用小波包变换处理器芯片，它适于单片实现或作为各类应用系统的引擎单元。在完成芯片设计的同时，利用ＳＹＮＯＰＳＹＳ公司和ＡＬＴＥＲＡ公司的设计软件，以ＡＬ－ＴＥＲＡ公司的现场可编程门阵列（ｆｉｅｌｄｐｒｏｇｒａｍｍａｂｌｅｇａｔｅａｒｒａｙ，ＦＰＧＡ）器件为基础完成了对芯片的电路仿真。
The hardware implementation of wavelet packet transform is studied. Aiming at the shortcomings of the existing schemes, such as wavelet transform hardware, shortcomings, such as long branchlet wavelet and high resolution series, the hardware architecture of wavelet packet transform based on double buffer storage is proposed. It has a certain degree of programmability and versatility. Based on this, a general-purpose wavelet packet transform processor chip is designed. It is suitable for single-chip implementation or as an engine unit of various application systems. At the same time of completing the chip design, the circuit simulation of the chip was finished based on AL-TERA field programmable gate array (FPGA) device by using the design software of SYNOPSYS and ALTERA.