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基于90 nm栅长的InP高电子迁移率晶体管(HEMT)工艺,研制了一款工作于130~140 GHz的MMIC低噪声放大器(LNA)。该款放大器采用三级级联的双电源拓扑结构,第一级电路在确保较低的输入回波损耗的同时优化了放大器的噪声,后两级则采用最大增益的匹配方式,保证了放大器具有良好的增益平坦度和较小的输出回波损耗。在片测试结果表明,在栅、漏极偏置电压分别为-0.25 V和3 V的工作条件下,该放大器在130~140 GHz工作频带内噪声系数小于6.5 dB,增益为18 dB±1.5 dB,输入电压驻波比小于2∶1,输出电压驻波比小于3∶1。芯片面积为1.70 mm×1.10 mm。该低噪声放大器有望应用于D波段的收发系统中。
Based on a 90-nm gate length InP high electron mobility transistor (HEMT) process, an MMIC LNA is developed that operates at 130 to 140 GHz. The amplifier uses three cascaded dual-supply topology, the first circuit to ensure low input return loss while optimizing the amplifier noise, the latter two are the use of maximum gain matching, to ensure that the amplifier has Good gain flatness and small output return loss. The on-chip test results show that the amplifier has a noise figure of less than 6.5 dB and a gain of 18 dB ± 1.5 dB over the 130 to 140 GHz operating band with a gate-to-drain bias of -0.25 V and 3 V, respectively , Input voltage standing wave ratio less than 2: 1, output voltage standing wave ratio less than 3: 1. The chip area is 1.70 mm × 1.10 mm. The low noise amplifier is expected to be used in the D-band transceiver system.