A 12 bit 100 MS/s pipelined analog to digital converter without calibration

• 作 者: 蔡小波 李福乐 张春 王志华
• 机 构: Institute of Microelectronics,Tsinghua University,
• 出 处: 半导体学报
• 发表日期: 2010年11期
• 关键词: converter analog calibration dissipation SFDR matching linearity capacitor switc

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC’s linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumption is 112 mW at a 1.8 V supply,including output drivers.The chip area is 3.51 mm~2,including pads.

A 1.8 V 12 bit 100 MS / s pipelined analog to digital converter (ADC) in a 0.18 μm complementary metal-oxide semiconductor process is presented. The first stage is a 3.5 bit structure to relax the capacitor matching requirements. A bootstrapped switch and a scaling down technique are used to improve the ADC’s linearity and save power dissipation, respectively. Here a 15.5 MHz input signal, the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS / s. power consumption is 112 mW at a 1.8 V supply, including output drivers. The chip area is 3.51 mm ~ 2, including pads.