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A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized.Some new circuit techniques are adopted to improve its performance.A dual-modulus prescaler(DMP) with low phase noise is realized with a kind of improved source-coupled logic(SCL) D-flip-flop(DFF) in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave(CMOS MS)-DFF in the asynchronous divider.A new more accurate wire-load model is used to realize the pulse-swallow counter(PS counter).Fabricated in a 0.18-μm CMOS process,the total chip size is 0.6×0.2 mm~2.The DMP in the proposed down-scaling circuit exhibits a low phase noise of-118.2 dBc/Hz at 10 kHz off the carrier frequency.At a supply voltage of 1.8 V,the power consumption of the down-scaling circuit’s core part is only 2.7 mW.
A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are designed to improve its performance. A dual-modulus prescaler (DMP ) with low phase noise is realized with a kind of improved source-coupled logic (SCL) D-flip-flop (DFF) in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave (CMOS MS) the asynchronous divider.A new more accurate wire-load model is used to realize the pulse-swallow counter (PS counter). Fabrication in a 0.18-μm CMOS process, the total chip size is 0.6 × 0.2 mm ~ 2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of -18.2 dBc / Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit’s core part is only 2.7 mW.