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本文简要介绍了几种结构的数字乘法器。着重讨论了以大规模集成电路为基础的并发结构数字乘法器的设计和性能。给出了并发结构四位数字乘法器的功能模拟结果及CMOS工艺版图。
This article briefly introduces several structures of digital multipliers. The design and performance of a concurrent digital multiplier based on a large scale integrated circuit are highlighted. The functional simulation results of four-digit digital multiplier with concurrent structure and the CMOS process layout are given.