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本文讨论了时钟信号的普遍描述和含时钟信号的触发器次态方程,并在此基础上提出了同步和异步时序电路的统一设计和分析理论。该理论的有效性已由实例予以证明。
This paper discusses the universal description of clock signals and the flip-flop equations of flip-flops with clock signals. Based on this, a unified design and analysis theory of synchronous and asynchronous timing circuits is proposed. The validity of this theory has been demonstrated by examples.