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CPCI总线是一种成熟全面的计算机总线,通过它主机可以方便地为DSP加载程序,进行调试和监控工作;另外还能在主机和DSP系统间完成高速数据传输工作。本文结合一个已经成功应用的设计,阐述了基于双状态机+Cache结构的主机接口设计,并给出了逻辑框图。利用PLX公司的PCI9656接口芯片,FPGA提供了高达90MB/s的主机访问DSP和SDRAM的速度。
CPCI bus is a mature and comprehensive computer bus, through its host can easily load the program for the DSP, debugging and monitoring work; in addition to the host and the DSP system to complete high-speed data transmission. In this paper, the design of a host computer that has been successfully applied is described, and the design of the host interface based on the dual-state + + cache structure is described. The logic block diagram is also given. Using PLX PCI9656 interface chip, FPGA provides up to 90MB / s host access DSP and SDRAM speed.