Design and implementation of a DSP with multi-level low power strategies for cochlear implants

• 作 者: 麦宋平
• 机 构: Department of Electronic Engineering,Tsinghua University,
• 出 处: High Technology Letters
• 发表日期: 2009年02期
• 关键词: cochlear processor partitioning Sampling isolation gating leaved targeting proto

This paper presents the design and implementation of a low power digital signal processor(THUCID-SP-1)targeting at application for cochlear implants.Multi-level low power strategies including algorithmoptimization,operand isolation,clock gating and memory partitioning are adopted in the processor designto reduce the power consumption.Experimental results show that the complexity of the Continuous Inter-leaved Sampling(CIS)algorithm is reduced by more than 80% and the power dissipation of the hardwarealone is reduced by about 25% with the low power methods.The THUCIDSP-l prototype,fabricated in0.18-μm standard CMOS process,consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.

This paper presents the design and implementation of a low power digital signal processor (THUCID-SP-1) targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are both in the processor designto reduce the power consumption. Experimental results show that the complexity of the Continuous Inter-leaved Sampling (CIS) algorithm is reduced by more than 80% and the power dissipation of the hardwarealone is reduced by about 25% with the low power methods. THUCIDSP-l prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.