论文部分内容阅读
时序是数字时序电路的核心,时序得不到满足将直接导致电路不能正常、稳定地工作。随着人们对系统数据吞吐量要求的成倍增加,芯片的规模和复杂度也在不断上升,此时,时序成为数字电路频率上升的瓶颈。时序违例往往导致芯片开发不能顺利进行甚至流片失败,这是不能接受的。从前端RTL代码到逻辑综合过程,研究了数字芯片设计中的时序优化方法,为数字电路工程师和研究人员提供有益的参考。
Timing is the core of the digital timing circuit, the timing is not satisfied will lead directly to the circuit can not be normal, stable work. As people’s requirements for system throughput increase exponentially, the size and complexity of the chip are also on the rise. At this point, the timing becomes a bottleneck in the rise of the digital circuit frequency. Timing violations often lead to chip development can not be smooth or even flow failure, it is unacceptable. From the front-end RTL code to the logic synthesis process, the timing optimization method in digital chip design is studied, which provides a useful reference for digital circuit engineers and researchers.