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本文研究了双极型电路传输延时的约束机理。用灵敏度分析法导出了ＥＣＬ电路传输延时的修正公式。指出：为了提高高速数字电路的集成密度，降低单元电路的功耗是必要的。在低功耗轻负载时，ＥＣＬ电路的高速特性主要取决于电路的上拉电阻及与其相关的器件电容和引线电容。功耗越低，负载电容越大，射随器级的下拉电阻和负载电容的影响越来越占主导地位。为了克服低耗问题，文中提出了一些相应对策，并给出了一种高速低耗的可行性电路结构──改进的ＣＭＬ（ＭＣＭＬ）电路。用ｍｗＳＰＩＣＥ仿真结果表明：单门功耗为１．５４ｍＷ时，平均时延可低速１５．２ｐｓ，０．９９ｍＷ时为１７．３ｐｓ，０．４９ｍＷ时为２８．５ｐｓ。负载电容在８～８００ｆＦ范围内时，Ｐｄ（功耗－延时）积比普通ＥＣＬ电路改善２．２～３．６倍。
This paper studies the constraint mechanism of the propagation delay in bipolar circuits. The sensitivity analysis method is used to derive the correction formula of transmission delay of ECL circuit. Pointed out: In order to improve the integrated density of high-speed digital circuits, reducing the power consumption of the unit circuit is necessary. At light loads with low power consumption, the high speed characteristic of the ECL circuit mainly depends on the pull-up resistance of the circuit and its associated device capacitance and lead capacitance. The lower the power consumption is, the larger the load capacitance is. The effect of emitter-follower pull-down resistors and load capacitors is becoming more and more dominant. In order to overcome the problem of low power consumption, some countermeasures are put forward in the article, and a feasible circuit structure of high speed and low power consumption is proposed, namely the improved CML (MCML) circuit. Using mSPICE simulation results show that: single-door 1.54mW power consumption, the average delay of low-speed 15.2ps, 0.99mW when the 17.3ps, 0.49mW 28.5ps. When the load capacitance is in the range of 8 to 800 fF, the Pd (power dissipation-delay) product is 2.2 to 3.6 times better than the conventional ECL circuit.