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本文叙述雷达和通信信号处理器中应用的一种可编程序 CCD 抽头延迟线。64级 CCD 延迟线(在每级抽头)已经用作二进制加权模拟相关器和带通滤波器。这种 CCD 是一种浅埋 n 型沟道器件,而基准码输入和存储所需要的单片逻辑电路是 NMOS 电路,试验结果表明,对于64位码米说,峰值—旁辩比接近理论值,线性良好,工作速度高(超过15兆赫)。已经实现了片上(On—ChiP)和信号电流的差分相减。
This article describes a programmable CCD tapped delay line used in radar and communications signal processors. The 64-stage CCD delay line (at each tap) has been used as a binary weighted analog correlator and band-pass filter. The CCD is a shallow buried n-type channel device, and the reference code input and memory required for the monolithic logic circuit is the NMOS circuit, the test results show that for the 64-bit code meter said peak - Parapair ratio close to the theoretical value Good linearity and high working speed (more than 15 MHz). Differential subtraction of On-ChiP and signal currents has been achieved.