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实现了一种用于心电信号采集的动态调整工作模式的低功耗24位Δ-ΣADC。采用3阶5位的调制器结构,高速模式下,SNR达到120.4dB,ENOB为19.71位;低速模式下,SNR为108.4dB,ENOB为17.71位。使用一种自适应的QRS波检测模块,ADC可以根据心电波形实时调整工作模式。针对典型心电信号,采用动态调整模式后的数据量可以压缩至非动态调整时的62.5%,平均功耗可以降低至101.5μW,是非动态调整时的66.7%。
A low-power 24-bit delta-sigma ADC for dynamic adjustment of ECG signals is implemented. Using a 3-order 5-bit modulator structure, the SNR achieves 120.4dB and ENOB is 19.71 bits in high-speed mode. The SNR is 108.4dB and ENOB is 17.71 bits in low-speed mode. Using an adaptive QRS detection module, the ADC can adjust the operating mode in real time based on the ECG waveform. For typical ECG signals, the amount of data in the dynamic adjustment mode can be reduced to 62.5% of the non-dynamic adjustment, the average power consumption can be reduced to 101.5μW, 66.7% when non-dynamic adjustment.